1. Field of the Invention
The present invention relates to computer processor systems and, more specifically, to a redundant multiprocessor system.
2. Description of the Prior Art
Address concentrating processor systems (such as the Cell processor system) provide power-efficient and cost-effective high-performance processing for a wide range of applications. Typically, such systems have been used in graphics-intensive applications, including the most demanding consumer systems, such as game consoles. Address concentrating processor systems are also useful in computationally-intense applications such as: cryptography, scientific simulation, fast-Fourier transforms (FFT), matrix operations and advanced avionics applications.
An address concentrating processor system is a scalable computational system that distributes computational functions over a hierarchy of individual processors. In an existing address concentrating processor system 10, as shown in FIG. 1, a plurality of processor units/special purpose engines (PU/SPE) 12 perform all of the computational functions of the system 10. Each pair of PU/SPE's 12 is coupled to a lowest-level address concentrating processor (AC2) 14, which collects and distributes commands to and from a higher level address concentrating processor (AC1) 16 to be performed by the individual PU/SPE's 12 to allow a process to be distributed across the two PU/SPE's 12 in an orderly manner. Similarly, each AC2 14 is coupled to a higher-level address concentrating processor (AC1) 16 that orders commands and snoops to the AC2's 14. Ultimately, a highest-level address concentrating processor (AC0) 18 orders commands and snoops to the AC1's 16, thereby ordering execution of the process across the entire system. The AC0 18 must process coherent commands while the AC1 16 can process non-coherent commands. The AC2's 14 can only pass commands and snoops up and down through the system
Such a processor system allows high performance distributed computing and is highly flexible, in that additional layers in the hierarchy can be added to increase the computational power of the system. Thus, such systems tend to be highly scalable, in that the number of attached PU/SPE's can be varied, to achieve a desired balance of power versus performance and price versus performance.
Because of their scalability and ability to handle complex computations, address concentrating processor systems could be useful in space and high altitude applications. However, because most systems sent into space cannot be accessed by technicians and because they are subject to radiation-induced errors, any computational system being sent into space (or used for other mission-critical applications) must have an inherent error detection and correction capability.
One type of error detection and correction system that is applied to memory devices such as registers is the triple voting system. In a triple voting system, each unit of data is stored in three separate memory locations and when accessed, each of the three memory locations is accessed simultaneously. The system compares each corresponding bit received from each memory location and, when one bit is different from the other two, accepts the value of the two agreeing bits as the result. The system will also rewrite the memory location that has the disagreeing bit with the accepted bit, thereby correcting the error in the memory location.
Unfortunately, systems developed for game applications often do not have an error detection and correction capability that is sufficient for space applications. Also, given that such systems are typically embodied on one or more computer chips, they cannot be modified so as to have such capability. For example, the Cell processor is a high frequency, manually placed, custom chip, the redesign of which is difficult to change. Thus, applying normal fault mitigation techniques, such as adding triple voting latches, to the internal design of the chip is impractical.
Therefore, there is a need for a system that allows error detection and correction capability to be applied to existing address concentrating processor systems.